Field of the Invention
The present invention relates to a protection circuit.
Description of the Related Art
In order to protect components that form a semiconductor circuit, various kinds of protection circuits are provided. Examples of such a protection circuit include: an overvoltage protection circuit configured to provide a circuit component with overvoltage protection; an overcurrent protection circuit configured to provide a circuit component with overcurrent protection, and the like. In addition, such protection circuit examples can be said to include a UVLO (Under Voltage LockOut) circuit that detects a UVLO condition in order to prevent a circuit from operating abnormally in a low voltage condition.
For example, an overcurrent protection circuit detects a current that flows through a circuit element to be protected, and compares the current thus detected with a predetermined threshold. When the detected current exceeds the threshold, protection processing is executed, examples of which include circuit operation suspension, current disconnection, and the like.
In some cases, multiple thresholds are set for such a protection circuit, in order to provide multilevel protection. For example, an overcurrent protection circuit mounted on a control circuit of a switching circuit detects a current that flows through a coil or a switching transistor. With such an arrangement, when the detected current exceeds a first threshold ITH1, the overcurrent protection circuit suspends the switching operation of the switching transistor in units defined by its switching period. When the detected current exceeds a second threshold ITH2 that is higher than the first threshold ITH1, the overcurrent protection circuit completely suspends the switching operation of the switching transistor M1.
In some cases, multiple desired thresholds are preferably set for such a protection circuit via an external circuit. FIG. 1 is a circuit diagram showing a protection circuit investigated by the present inventors. A protection circuit 40 is configured as an overcurrent protection circuit for a DC/DC converter. The protection circuit 40 is built into a control circuit 10. The control circuit 10 forms a switching power supply circuit (which will simply be referred to as the “power supply circuit”) 2 together with an output circuit 20. The output circuit 20 includes a switching circuit 102, an inductor L1, an output capacitor C1, and resistors R11 and R12.
The control circuit 10 includes a switching circuit 102. In addition, the control circuit 10 further includes a controller 104 that controls the switching circuit 102, and an overcurrent protection circuit 40. A feedback voltage VFB that corresponds to an output voltage VOUT is input to a feedback (FB) terminal of the control circuit 10.
The controller 104 adjusts the duty ratio that is supplied to a high-side transistor MH and a low-side transistor ML of the switching circuit 102 such that the feedback voltage VFB matches a predetermined target voltage.
The overcurrent protection circuit 40 detects a current IS that flows through the output circuit 20, and compares the current IS thus detected with multiple thresholds ITH1 and ITH2. The overcurrent protection circuit 40 includes a first detector 402, a second detector 404, a first memory 406, a second memory 408, and an interface circuit 410.
The first memory 406 and the second memory 408 store setting data D1 that indicates the first threshold ITH1 and setting data D2 that indicates the second threshold ITH2, respectively. The first detector 402 compares the detected current IS with the threshold ITH1 that corresponds to the setting data D1 stored in the first memory 406. The second detector 404 compares the detected current IS with the threshold ITH2 that corresponds to the setting data D2 stored in the second memory 408. The interface circuit 410 receives the setting data D1 and D2 from an external processor, and writes the setting data D1 and D2 thus received in the first memory 406 and the second memory 408, respectively. The controller 104 performs protection processing that is changed according to the detection results provided by the first detector 402 and the second detector 404.
It should be noted that the overcurrent protection circuit 40 shown in FIG. 1 and the control circuit 10 including such an overcurrent protection circuit 40 should not be regarded as conventional techniques (Prior Art).
As a result obtained by investigating such a protection circuit, the present inventor has come to recognize the following problem.
In the overcurrent protection circuit 40 shown in FIG. 1, the first memory 406 and the second memory 408 are configured as memory spaces defined in the same sector in a single memory unit mounted on a single chip. For example, the first memory 406 and the second memory 408 may be defined as adjacent addresses. In this case, the processor 4 writes the setting data D1 and D2 to the corresponding memory 406 and 408 at substantially the same time in a single writing sequence.
Accordingly, in a case in which transmission error occurs in the writing sequence, the interface circuit 410 has the potential to receive false values with respect to both the setting data D1 and D2. Also, in a case in which the first memory 406 and the second memory 408 are exposed to strong electromagnetic noise or cosmic rays in the writing sequence or after the writing sequence, such an arrangement has the potential to store false values even if the interface circuit 410 has received the setting data D1 and D2 normally.
As described above, with the overcurrent protection circuit 40 shown in FIG. 1, there is a risk of losing the multiple protection functions provided by the first detector 402 and the second detector 404 at the same time due to a single error-generating factor.